CVE-2022-42336
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Mishandling of guest SSBD selection on AMD hardware The current logic to set SSBD on AMD Family 17h and Hygon Family 18h processors requires that the…
rank 10 = 0 + 8 + 0 + 2 + 0
rank@v1 · backlog
Someone is already using it
CISA KEV catalog · public proof-of-concept · FIRST EPSS
EPSS 0.00264 · without this subject the record ranks 10
What it costs you if it fires
NVD CVSS base score, then the CNA's own
CVSS 3.3, from NVD · without this subject the record ranks 2
It is getting worse, not staying still
FIRST EPSS series, rescorings and bad loads removed
no persisting rise in 365 days · without this subject the record ranks 10
How much of the world it touches
NVD CPE configurations
1 product in the CPE ranges · without this subject the record ranks 8
Someone else already set the date
CISA KEV remediation due date
no CISA due date · without this subject the record ranks 10
$3,170 = $4.99M incident cost x 0.24048551839932833 exposure x 0.00264 likelihood
udv@v1 · unaudited · wrong for you until you say what you run
$4.99M is the cost of a breach that happened, from IBM Cost of a Data Breach Report 2026, global average. It is not the value of any asset of yours. That average already covers breaches of every severity, so scaling it by exposure understates a partial-impact record. That is an assumption, not a measurement. Your own asset value goes in the decision record.
Hindsight · the state
Foresight · where to check next
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CISA KEV & Federal Remediation Deadline from the record and CISA
The fix, and how long it's been waiting.
Exploit Status & Known PoCs a ladder, not a score
Current rung: Nothing observed in held sources.
- RUNG 1Nothing observed in held sources
- RUNG 2Proof-of-concept published
- RUNG 3Exploited in the wild · CISA KEV listed
- RUNG 4Ransomware campaign use known
A rung lights from a row in the index, never from an assessment. "Held sources" is the true scope of the claim: this index reads the CVE record, NVD, CISA KEV, FIRST's EPSS and public proof-of-concept repositories, and it does not observe attacks.
What it is stated by the CNA
Mishandling of guest SSBD selection on AMD hardware The current logic to set SSBD on AMD Family 17h and Hygon Family 18h processors requires that the setting of SSBD is coordinated at a core level, as the setting is shared between threads. Logic was introduced to keep track of how many threads require SSBD active in order to coordinate it, such logic relies on using a per-core counter of threads that have SSBD active. When running on the mentioned hardware, it's possible for a guest to under or overflow the thread counter, because each write to VIRT_SPEC_CTRL.SSBD by the guest gets propagated to the helper that does the per-core active accounting. receipt
Read the rest of the CNA's description
Underflowing the counter causes the value to get saturated, and thus attempts for guests running on the same core to set SSBD won't have effect because the hypervisor assumes it's already active.
NVD's analysis a second authority
- severity
- 3.3 CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:N/I:L/A:N
- affected versions
- xen 4.17
- also scored by
- 3.3 CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:N/I:L/A:N
check it yourself xenbits.xenproject.org lists.fedoraproject.org receipt
Movement the material steps
Show all 16 observations
16 observations held. A highlighted step crossed a promotion threshold. A step marked with a scoring model moved because the instrument was replaced, not because the vulnerability changed. receipt
The full biography
The record had been public for 3 years when this index was last written.
Siblings and hubs
Records related to this one
None. No alias set, and nothing in the corpus cites this identifier or shares its product family within 60 days.
Browse the index from here
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What usually comes next
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